Clock-gating is a widely adopted technique for deactivating particular resources within an integrated circuit (IC). A clock gating circuit deactivates an IC resource by gating a clock signal provided to the resource. In response to an active clock enable signal, the clock gating circuit passes the clock signal to a target resource. Conversely, the clock gating circuit inhibits or blocks the clock signal from reaching the target resource when the clock enable signal is inactive.
In some cases, a clock gating circuit receives more than one clock enable signal. Each clock enable signal facilitates clock gating during a particular application. For example, one clock enable signal gates functional clocking of an IC resource during normal operation of the IC and a different clock enable signal gates test clocking of the IC resource during testing of the IC. Conventional multi-enabled clock gating circuits include a clock enable selection mechanism such as a multiplexer or other combinatorial logic. The clock enable selection mechanism selects one of a plurality of clock enable signals for activating clock gating during a particular application.
However, conventional multi-enabled clock gating circuits, particularly the clock enable selection mechanisms thereof, add delay to the clock enable signal paths. Conventional clock enable selection mechanisms subject clock enable signals to additional signal propagation delay not experienced by the internal clock signal to be gated. That is, the clock enable signals are processed by the clock enable selection mechanism before gating the internal clock signal. Unlike the clock enable signals, the clock signal to be gated does not propagate through the clock enable selection mechanism, and thus, is not subjected to the corresponding additional delay.
The additional delay incurred by the clock enable signals increases the setup time associated with the signals. That is, the clock enable signals should arrive at the clock gating circuit sufficiently in advance of the clock signal to be gated. Otherwise, the gated clock signal will be skewed. Circuits downstream from the clock gating circuit may function unpredictably in response to a skewed clock signal. Clock-gating induced skew can be reduced by increasing setup time associated with the clock enable signals. However, increased setup time adversely affects IC performance, i.e., the maximum attainable operating frequency of the IC is decreased. This is of particular concern for clock enable signals that gate functional clocking of an IC resource during normal operation of the IC.